1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices and methods of manufacturing the semiconductor memory devices. More particularly, example embodiments of the present invention relate to non-volatile semiconductor memory devices including a dielectric layer having a high dielectric constant, and methods of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices may be generally divided into volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile semiconductor memory devices such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device lose data stored therein when power is turned off. Non-volatile semiconductor memory devices such as flash memory devices and Read-only memory (ROM) have the ability to maintain data stored therein even when power is turned off. Recently, demand for flash memory devices has increased.
In general, a flash memory device may have a memory cell to store data. The memory cell may have a stacked gate structure, including a floating gate formed by forming a tunnel oxide layer on a silicon substrate, and a control gate formed by forming a dielectric layer on the floating gate. Data may be stored in the memory cell by injecting electrons into the floating gate and extracting electrons from the floating gate by applying appropriate voltages to the control gate and the substrate. The dielectric layer may maintain electrical characteristics of charges that may be stored in the floating gate, and may allow voltage of the control gate to flow to the floating gate.
FIG. 1 is a cross-sectional view illustrating a non-volatile semiconductor memory device of the prior art.
Referring to FIG. 1, the non-volatile semiconductor memory device may include a tunnel oxide layer 15 formed on a semiconductor substrate 10 having an isolation layer (not shown). A floating gate 20 may be formed on the tunnel oxide layer 15, a dielectric layer 40 having an ONO (Oxide/Nitride/Oxide) structure may be formed on the floating gate 20, and a control gate 45 may be formed on the dielectric layer 40. The dielectric layer 40 may have a sequentially stacked first oxide layer 25, nitride layer 30, and second oxide layer 35. The floating gate 20 and the control gate 45 may be formed of polysilicon.
The non-volatile semiconductor memory device may store data by injecting electrons into the floating gate 20 or extracting electrons from the floating gate 20 by applying appropriate voltages to the control gate 45 and the semiconductor substrate 10. The dielectric layer 40 may maintain electrical characteristics of charges that may be stored in the floating gate 20, and allow the voltage of the control gate 45 to flow to the floating gate 20. However, in the case of the non-volatile semiconductor memory device having an ONO structure as described above, the dielectric layer may have multiple layers of the oxide layer and the nitride layer, which may create insufficient dielectric constant required for the non-volatile semiconductor memory device. Such a structure may require complicated processes to form the dielectric layer. Additionally, stacking the multiple layers to form the dielectric layer may increase a thickness of the dielectric layer.
Conventional art discloses a semiconductor device which may include a dielectric layer formed of aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum pentoxide (Ta2O5) or vanadium pentoxide (V2O5) doped with Group IV elements, such as zirconium (Zr), silicon (Si), titanium (Ti) and hafnium (Hf). Conventional art also discloses a floating gate memory device which may include a dielectric layer having aluminum oxide or yttrium oxide, or aluminum oxide, yttrium oxide and tantalum pentoxide doped with Group IV elements such as zirconium or silicon. However, in the case of a non-volatile semiconductor memory device including a dielectric layer with metal oxide doped with Group IV elements, a band gap of the metal oxide decreases, which may deteriorate electrical characteristics of the dielectric layer, even though a dielectric constant of the dielectric layer may increase.